HW Protocols

Parallel interface transfer multiple bits at the same time, require buses of data (8,16, or more wires)
e.g. To transmit two bytes every clock pulse, 17 wires are used (16-data, 1-clock)
Out0 --> In0
Out1 --> In1
...,  
Out15--> In15      
Clk

Serial Interface stream data, one bit at a time.
OUTCLK - b0-b1-b2-b3...-b15 INCLK
E.g. SPI, I2C, USB(Universal Serial Bus), Ethernet.
Serial Bus has two wires, TX and RX crossed over.
RX    - TX
TX    - RX
GND - GND

A. Synchronous Serial: Always pairs data lines sharing common Clock. E.g. SPI, and I2C
B. Asychronous Serial: Data transferred without external clock. Helps minimize wires, pins, but requires additional effort to ensure reliable data tx/rx.
In computer system, everything should be synchronized to single clock. Then how Asychronous

Issue: Serial communication works without common clock?
Ans: It has certain mechanism to ensure error free data tx/rx, especially start.stop bits.

Data bits: 5-9 bits per packet. Both devices need to agree to data length and endianness before transmission begins.
Synchronization bits: 2-3 special bits, start bit(1) and stop bit(1-2). Start bit- data line 1->0, Stop bit hold data line high.
Parity bits: Odd/Even. number of set bits in data bits. Optional, slows down data transfer, require both sender/receiver implement error handling.
Baud rate: how fast data is sent over a serial line. bits-per-second. Practically upto 115200 bps
Frame formation: START_BIT(1) - Data Bits (8) - PARITY(1)-STOP_BIT(1)
E.g. 115200 bps baud rate, 10 bits are send every byte of data. Thus, 115200 bits per seconds sending 115200 Byte/Second data (8 bits per 10 bits of transmission).

In asynchronous serial, random amount of data can be sent in either direction any time.

UART: [Universal Asynchronous Receiver Transmitter]
To convert data on parallel bus to/from serial interface. Commonly found inside microcontrollers, also available as standalone IC.
More advanced UARTs may put received data into a buffer[as small as a few bits, or as large as thousands of bytes], where it stays until the microcontroller gets it. UARTs usually releases buffered data on a FIFO basis. Key, Both devices on a serial bus must be configured to use the exact same protocols

Asynchronous Serial is designed for communication between exactly two devices. If more are connected, bus contention can come in.

Bus Contention: Lets say two device trying to get TX control at same time, either both or none may be able to transmit.

SPI- Serial Peripheral Interface
It is synchronous solution to overhead issue in using asynchronous serial communication.
Usage: send data between micro-controller and peripherals (e.g. SD cards, Flash etc.)
+ faster than asynchronous serial bus, supports multiple slave. good for high data rate, is full duplex.
- can NOT send random amount of data when wish, no slave-slave communication, must go through master.
- Require separate Slave Select (SS) line for each slave device-> Increase number of Pins. Each new slave require additional SS pin on master.

It has separate data and clock signal. The clock signal tells receiver to expect data as soon as there is transition on clock signal. Receiver does not look for start/stop bits.

Only one side generates clock, called master clock. Always single master, possible multiple slaves.
Master keeps generating pre-arranged number of clock on which slave can send data. The data from Master->Slave is sent on MOSI [Master Out Slave In], and reverse on MISO [Master In Slave Out].

Master should know in advance, when and how much data slave wants to transfer.
SPI is used to talk to sensors etc having pre-defined command structure. So easy to know how much data to expect and when.

It is full-duplex(separate send and receive), has 4 pins ( 3 for data, 1 for slave select):

• SerialCLK
• MOSI [Master Out Slave In]
• MISO [Master In Slave Out]
• SlaveSelect

Multiple slaves can share 3 wires(data), but each slave require separate signal from master to select.

Each slave device has 8-bit shift register.

During master communication with slave, the registers of master and slave are connected in a ring so that both master and slave simultaneously transmit and receive(full-duplex). If half duplex communication is required, each device discards bytes received in transmit phase and generates dummy bytes in receive phase.

A pair (CPOL, CPHA), 4 values, define SPI Mode.
CPOL: Clock polarity. Selects level of SerialCLK line before and after data transfer.
CPHA: Clock phase. Determines edge of clock on which slave latches input-data bits and shifts output data bits out.

CPHA (=0/1) input data bits latch onto each odd/even clock edge, and output data bits latch onto even/odd clock edge. A slave considers transfer complete after 8th bit latches itself.

Multiple slaves can be connected in SPI,
Scheme 1: Multiple Slave Select lines. To talk to Slave1, master makes SS1 low, keep rest SSn low.
Scheme 2: Daisy-chain slaves, i.e. MISO of SS1 going to MOSI of SS2 and so on. Data is chained, so overflows from SS1 to SS2 and so on. The first data sent goes to last slave.

I2C: Inter-Integrated Circuit
One master can communicate with all slaves. Master devices can not talk to each other and take turns for using bus.
For every 8 bit of data, 1 bit of metadata- ACK/NACK overhead.
Each I2C has SCL(clock) and SDA(data).
Current bus master generate clock.
Clock Stretching: Some slave can force clock low to delay master sending more data.
Unlike UART, SPI, I2C driver can only pull signal line LOW, not high. Thus no bus contention where one tries to pull high, other tries to pull low.

Data Rate: Asychronous < I2C[100kHz or 400kHz] < SPI
HW Complexity: SPI<I2C>AsyncSerial


References

SPI
Serial Communication
Coding SPI SW